--***************************************************************
--* File         : TB_UB2BCD.vhd                                *
--* Created      : 2008/01/22 Osamu Kawashima                   *
--* Modified     : Time-stamp: <08/01/22 02:32:16 kawasan>      *
--*                                                             *
--* Test-Bench                                                  *
--* 8bit-Data -> 3-BCD                                          *
--*                                                             *
--* Copyright 2008 Osamu Kawashima. all rights reserved         *
--***************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use std.textio.all;
use ieee.std_logic_textio.all;

entity TB_UB2BCD is end;

architecture behavior of TB_UB2BCD is
    
	component UB2BCD
	port (
		RESET           : in    std_logic;
		SYSCLK          : in    std_logic;
		BIN_I           : in    std_logic_vector(7 downto 0);
		START           : in    std_logic;

		STOP            : out   std_logic;
		BCD_O           : out   std_logic_vector(11 downto 0)
	);
	end component;

	constant ZERO32         : std_logic_vector(31 downto 0) := (others=>'0');

	constant WT1            : Time := 10 ns;
	constant WT_DELAY       : Time := 1 ns;
	constant WT_IDLE        : Time := 100 ns;
	constant CLK_CYCLE      : Time := 21 ns;	-- about 48MHz

	signal RESET            : std_logic := '1';
	signal SYSCLK           : std_logic := '0';
	signal BIN_I            : std_logic_vector(7 downto 0) := (others=>'0');
	signal START            : std_logic := '0';
	signal STOP             : std_logic := '0';
	signal BCD_O            : std_logic_vector(11 downto 0) := (others=>'0');

begin
    
	uUB2BCD : UB2BCD
	port map (
		RESET           => RESET,
		SYSCLK          => SYSCLK,
		BIN_I           => BIN_I,
		START           => START,

		STOP            => STOP,
		BCD_O           => BCD_O
	);

	process begin
		SYSCLK <= '0';
		wait for CLK_CYCLE/2;
		SYSCLK <= '1';
		wait for CLK_CYCLE/2;
	end process;

	process
		variable ln         : line;
	begin
		-- Reset
		wait for WT_DELAY+WT_IDLE;
		RESET <= '0';

		---[No.1]---
		wait for WT_IDLE;
		-- Start
		wait until SYSCLK'event and SYSCLK='1';
		wait for WT_DELAY;
		BIN_I <= x"07";
		START <= '1';
		wait for CLK_CYCLE;
		START <= '0';
		-- Stop
		wait until STOP'event and STOP='1';
		wait for WT_IDLE;
		write(ln, string'("BIN_I, BCD_O = "));
		hwrite(ln, BIN_I);
		write(ln, string'(", "));
		hwrite(ln, BCD_O);
		writeline(output, ln);

		---[No.2]---
		wait for WT_IDLE;
		-- Start
		wait until SYSCLK'event and SYSCLK='1';
		wait for WT_DELAY;
		BIN_I <= x"FF";
		START <= '1';
		wait for CLK_CYCLE;
		START <= '0';
		-- Stop
		wait until STOP'event and STOP='1';
		wait for WT_IDLE;
		write(ln, string'("BIN_I, BCD_O = "));
		hwrite(ln, BIN_I);
		write(ln, string'(", "));
		hwrite(ln, BCD_O);
		writeline(output, ln);

		---[No.3]---
		wait for WT_IDLE;
		-- Start
		wait until SYSCLK'event and SYSCLK='1';
		wait for WT_DELAY;
		BIN_I <= x"7B";
		START <= '1';
		wait for CLK_CYCLE;
		START <= '0';
		-- Stop
		wait until STOP'event and STOP='1';
		wait for WT_IDLE;
		write(ln, string'("BIN_I, BCD_O = "));
		hwrite(ln, BIN_I);
		write(ln, string'(", "));
		hwrite(ln, BCD_O);
		writeline(output, ln);

		-- End
		write(ln, string'("--- End of Test-Bench. ---"));
		writeline(output, ln);
		wait;
	end process;

end behavior;