--***************************************************************
--* File	: TB_DIV32U.vhd					*
--* Created	: 2007/09/24 Osamu Kawashima			*
--* Modified	:						*
--*								*
--* Simulation DIV32U.vhd					*
--*								*
--* Copyright 2007 Osamu Kawashima. all rights reserved		*
--***************************************************************

library ieee;
use ieee.std_logic_1164.all;

entity TB_DIV32U is
	generic (
		DAT_SIZE : integer := 32
	);
end;

architecture behavior of TB_DIV32U is
    
	component DIV32U
	generic (
		DAT_SIZE : integer := 32
	);
	port (
		RESET		: in    std_logic;
		SYSCLK		: in    std_logic;
		DIVIDEND	: in    std_logic_vector(DAT_SIZE-1 downto 0);
		DIVISOR		: in    std_logic_vector(DAT_SIZE-1 downto 0);
		START		: in    std_logic;

		STOP		: out   std_logic;
		DATQ		: out   std_logic_vector(DAT_SIZE-1 downto 0);
		DATM		: out   std_logic_vector(DAT_SIZE-1 downto 0)
	);
	end component;

	constant DELAY		: Time := 1 ns;
	constant CLK_CYCLE	: Time := 20 ns;		-- about 48MHz
	constant WT1		: Time := CLK_CYCLE*2;
	constant WT2		: Time := CLK_CYCLE*20;

	signal	RESET		: std_logic := '1';
	signal	SYSCLK		: std_logic := '0';
	signal	DIVIDEND	: std_logic_vector(DAT_SIZE-1 downto 0) := (others=>'0');
	signal	DIVISOR		: std_logic_vector(DAT_SIZE-1 downto 0) := (others=>'0');
	signal	START		: std_logic := '0';
	signal	STOP		: std_logic := '0';
	signal	DATQ		: std_logic_vector(DAT_SIZE-1 downto 0) := (others=>'0');
	signal	DATM		: std_logic_vector(DAT_SIZE-1 downto 0) := (others=>'0');
    
begin
    
	uDIV32U : DIV32U
	generic map (
		DAT_SIZE => 32
	)
	port map (
		RESET		=> RESET,
		SYSCLK		=> SYSCLK,
		DIVIDEND	=> DIVIDEND,
		DIVISOR		=> DIVISOR,
		START		=> START,
		STOP		=> STOP,
		DATQ		=> DATQ,
		DATM		=> DATM
	);

	process begin
		SYSCLK <= '1';
		wait for CLK_CYCLE/2;
		SYSCLK <= '0';
		wait for CLK_CYCLE/2;
	end process;

	process begin
		-- Reset
		wait for DELAY+WT1;
		RESET   <= '0';

		--- [No.1 : 255/5=51(0) -> 33H(0H)] ---
		-- Set
		DIVIDEND <= x"000000FF";
		DIVISOR  <= x"00000005";

		-- Start
		wait for WT1;
		START    <= '1';
		wait for CLK_CYCLE;
		START    <= '0';

		--- [No.2 : 501/5=100(1) -> 64H(1H)] ---
		wait for 0.7 us;
		-- Set
		DIVIDEND <= x"000001F5";
		DIVISOR  <= x"00000005";

		-- Start
		wait for WT1;
		START    <= '1';
		wait for CLK_CYCLE;
		START    <= '0';

		-- End
		wait;
	end process;

end behavior;