--***************************************************************
--* File	: DIV32U.vhd					*
--* Created	: 2007/09/24 Osamu Kawashima			*
--* Modified	:						*
--*								*
--* 32bit/32bit Unsigned Division				*
--*								*
--* Copyright 2007 Osamu Kawashima. all rights reserved		*
--***************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity DIV32U is
	generic (
		DAT_SIZE : integer := 32
	);
	port (
		RESET		: in    std_logic;
		SYSCLK		: in    std_logic;
		DIVIDEND	: in    std_logic_vector(DAT_SIZE-1 downto 0);
		DIVISOR		: in    std_logic_vector(DAT_SIZE-1 downto 0);
		START		: in    std_logic;

		STOP		: out   std_logic;
		DATQ		: out   std_logic_vector(DAT_SIZE-1 downto 0);
		DATM		: out   std_logic_vector(DAT_SIZE-1 downto 0)
	);
end DIV32U;

architecture RTL of DIV32U is

	constant DAT_ZERO	: std_logic_vector(DAT_SIZE-1 downto 0) := (others=>'0');
	constant DAT_FULL	: std_logic_vector(DAT_SIZE-1 downto 0) := (others=>'1');

	type STATE is (STANDBY, LOAD, RUN);
	signal current_state	: STATE;

	signal bitcnt		: std_logic_vector(DAT_SIZE-2 downto 0);
	signal stop_is		: std_logic;
	signal datout_is	: std_logic_vector(DAT_SIZE-1 downto 0);
	signal mod_carry	: std_logic;
	signal mod_is		: std_logic_vector(DAT_SIZE-1 downto 0);
	signal mod_sub		: std_logic_vector(DAT_SIZE-1 downto 0);
	signal cnt_end		: std_logic;
	signal cmp_result	: std_logic;

begin

	-- State-Machine
	process (SYSCLK, RESET)
	begin
		if RESET = '1' then
			current_state <= STANDBY;
			stop_is <= '1';
			bitcnt <= (others=>'1');
			datout_is <= (others=>'0');
			mod_carry <= '0';
			mod_is <= (others=>'0');
		elsif SYSCLK'event and SYSCLK = '1' then
			case current_state is
			when STANDBY =>
				if START = '1' then
					current_state <= LOAD;
					stop_is <= '0';
				else
					stop_is <= '1';
				end if;

			when LOAD =>
				current_state <= RUN;

				mod_carry <= DAT_ZERO(DAT_SIZE-1);
				mod_is <= DAT_ZERO(DAT_SIZE-2 downto 0) & DIVIDEND(DAT_SIZE-1);
				datout_is <= DIVIDEND(DAT_SIZE-2 downto 0) & cmp_result;
				bitcnt <= (others=>'1');

			when RUN =>
				if cnt_end = '1' then
					current_state <= STANDBY;
					stop_is <= '1';
				end if;

				if cmp_result = '1' then
					mod_carry <= mod_sub(DAT_SIZE-1);
					mod_is(DAT_SIZE-1 downto 1) <= mod_sub(DAT_SIZE-2 downto 0);
				else
					mod_carry <= mod_is(DAT_SIZE-1);
					mod_is(DAT_SIZE-1 downto 1) <= mod_is(DAT_SIZE-2 downto 0);
				end if;
				mod_is(0) <= datout_is(DAT_SIZE-1);
				datout_is <= datout_is(DAT_SIZE-2 downto 0) & cmp_result;
				bitcnt <= '0' & bitcnt(DAT_SIZE-2 downto 1);
			end case;
		end if;
	end process;

	--
	cnt_end <= '1' when bitcnt = 0 else '0';
	cmp_result <= '1' when mod_is >= DIVISOR else '0';
	mod_sub <= mod_is - DIVISOR;

	--
	STOP <= stop_is;
	DATQ <= datout_is;
	DATM <= mod_carry & mod_is(DAT_SIZE-1 downto 1);

end RTL;