--***************************************************************
--* File         : TB_CTLWB.vhd                                 *
--* Created      : 2008/02/28-03:49 kawasan                     *
--* Modified     : Time-stamp: <08/02/28 18:52:02 kawasan>      *
--*								*
--* Test-Bench                                                  *
--* Controller WISHBONE-I/F                                     *
--*								*
--* Copyright 2008 Osamu Kawashima. all rights reserved		*
--***************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use std.textio.all;
use ieee.std_logic_textio.all;

entity TB_CTLWB is end;

architecture behavior of TB_CTLWB is
    
	component CTLWB
	port (
		-- WISHBONE MASTER interface:
		WB_CLK_I        : in    std_logic;
		WB_RST_I        : in    std_logic;
		WB_ADR_O        : out   std_logic_vector(31 downto 0);
		WB_DAT_I        : in    std_logic_vector(31 downto 0);
		WB_DAT_O        : out   std_logic_vector(31 downto 0);
		WB_WE_O         : out   std_logic;
		WB_SEL_O        : out   std_logic_vector(3 downto 0);
		WB_STB_O        : out   std_logic;
		WB_ACK_I        : in    std_logic;

		-- Other port interface:
		ADR             : in    std_logic_vector(31 downto 0);
		DAT_I           : in    std_logic_vector(31 downto 0);
		DAT_O           : out   std_logic_vector(31 downto 0);
		WE              : in    std_logic;
		SIZE            : in    std_logic_vector(1 downto 0);
		GO              : in    std_logic;
		DONE            : out   std_logic
	);
	end component;

	constant ZERO32         : std_logic_vector(31 downto 0) := (others=>'0');

	constant WT1            : Time := 10 ns;
	constant WT_DELAY       : Time := 1 ns;
	constant WT_IDLE        : Time := 100 ns;
	constant CLK_CYCLE      : Time := 21 ns;	-- about 48MHz
	constant BPS_CYCLE      : Time := 2 us;		-- 500Kbps


	signal WB_CLK_I         : std_logic := '0';
	signal WB_RST_I         : std_logic := '1';
	signal WB_ADR_O         : std_logic_vector(31 downto 0) := (others=>'0');
	signal WB_DAT_I         : std_logic_vector(31 downto 0) := (others=>'0');
	signal WB_DAT_O         : std_logic_vector(31 downto 0) := (others=>'0');
	signal WB_WE_O          : std_logic := '0';
	signal WB_SEL_O         : std_logic_vector(3 downto 0) := (others=>'0');
	signal WB_STB_O         : std_logic := '0';
	signal WB_ACK_I         : std_logic := '0';
	signal ADR              : std_logic_vector(31 downto 0) := (others=>'0');
	signal DAT_I            : std_logic_vector(31 downto 0) := (others=>'0');
	signal DAT_O            : std_logic_vector(31 downto 0) := (others=>'0');
	signal WE               : std_logic := '0';
	signal SIZE             : std_logic_vector(1 downto 0) := (others=>'0');
	signal GO               : std_logic := '0';
	signal DONE             : std_logic := '0';

	signal reset            : std_logic := '1';

begin
    
	uCTLWB : CTLWB
	port map (
		-- WISHBONE MASTER interface:
		WB_CLK_I        => WB_CLK_I,
		WB_RST_I        => WB_RST_I,
		WB_ADR_O        => WB_ADR_O,
		WB_DAT_I        => WB_DAT_I,
		WB_DAT_O        => WB_DAT_O,
		WB_WE_O         => WB_WE_O,
		WB_SEL_O        => WB_SEL_O,
		WB_STB_O        => WB_STB_O,
		WB_ACK_I        => WB_ACK_I,

		-- Other port interface:
		ADR             => ADR,
		DAT_I           => DAT_I,
		DAT_O           => DAT_O,
		WE              => WE,
		SIZE            => SIZE,
		GO              => GO,
		DONE            => DONE
	);

	process begin
		WB_CLK_I <= '0';
		wait for CLK_CYCLE/2;
		WB_CLK_I <= '1';
		wait for CLK_CYCLE/2;
	end process;

	WB_RST_I <= reset;

	process
		variable ln         : line;
	begin
		-- Reset
		wait for WT_DELAY+WT_IDLE;
		reset <= '0';
		wait for WT_IDLE;

		-- Read (Add=0x01234567, 1Byte)
		WB_DAT_I <= x"11223344";
		wait for CLK_CYCLE;
		ADR <= x"01234567";
		DAT_I <= x"00000000";
		WE <= '0';
		SIZE <= "00";
		wait for CLK_CYCLE;
		GO <= '1';
		wait for CLK_CYCLE;
		GO <= '0';
		wait for WT_IDLE;
		wait until WB_CLK_I'event and WB_CLK_I='1';
		wait for WT_DELAY;

		-- Read (Add=0x87654321, 4Byte, 2pls)
		WB_DAT_I <= x"22334455";
		wait for CLK_CYCLE;
		ADR <= x"87654321";
		DAT_I <= x"00000000";
		WE <= '0';
		SIZE <= "10";
		wait for CLK_CYCLE;
		GO <= '1';
		wait for CLK_CYCLE;
		GO <= '0';
		wait for CLK_CYCLE;
		wait for WT_IDLE;
		wait until WB_CLK_I'event and WB_CLK_I='1';
		wait for WT_DELAY;

		-- Write (Add=0x34567890, Dat=0x000055AA, 2Byte, 3pls)
		WB_DAT_I <= x"44556677";
		wait for CLK_CYCLE;
		ADR <= x"34567890";
		DAT_I <= x"123455AA";
		WE <= '1';
		SIZE <= "01";
		wait for CLK_CYCLE;
		GO <= '1';
		wait for CLK_CYCLE;
		GO <= '0';
		wait for CLK_CYCLE;
		wait for CLK_CYCLE;
		wait for WT_IDLE;
		wait until WB_CLK_I'event and WB_CLK_I='1';
		wait for WT_DELAY;

		-- End
		write(ln, string'("--- End of Test-Bench. ---"));
		writeline(output, ln);
		wait;
	end process;

	process begin
		WB_ACK_I <= '0';

		-- Read (Add=0x01234567, 1Byte)
		wait until WB_STB_O'event and WB_STB_O='1';
		wait for WT_DELAY;
		WB_ACK_I <= '1';
		wait until WB_STB_O'event and WB_STB_O='0';
		wait for WT_DELAY;
		WB_ACK_I <= '0';

		-- Read (Add=0x87654321, 4Byte, 2pls)
		wait until WB_STB_O'event and WB_STB_O='1';
		wait until WB_CLK_I'event and WB_CLK_I='1';
		wait for WT_DELAY;
		WB_ACK_I <= '1';
		wait until WB_STB_O'event and WB_STB_O='0';
		wait for WT_DELAY;
		WB_ACK_I <= '0';

		-- Write (Add=0x34567890, Dat=0x000055AA, 2Byte, 3pls)
		wait until WB_STB_O'event and WB_STB_O='1';
		wait until WB_CLK_I'event and WB_CLK_I='1';
		wait until WB_CLK_I'event and WB_CLK_I='1';
		wait for WT_DELAY;
		WB_ACK_I <= '1';
		wait until WB_STB_O'event and WB_STB_O='0';
		wait for WT_DELAY;
		WB_ACK_I <= '0';

	end process;

end behavior;